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M50LPW116
16 Mbit (2Mb x8, Boot Block) 3V Supply Low Pin Count Flash Memory
PRELIMINARY DATA
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SUPPLY VOLTAGE - VCC = 3V to 3.6V for Program, Erase and Read Operations
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- VPP = 12V for Fast Program and Fast Erase TWO INTERFACES - Low Pin Count (LPC) Standard Interface for embedded operation with PC Chipsets. - Address/Address Multiplexed (A/A Mux) Interface for programming equipment compatibility.
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LOW PIN COUNT (LPC) HARDWARE INTERFACE MODE - 5 Signal Communication Interface supporting Read and Write Operations - Hardware Write Protect Pins for Block Protection - Register Based Read and Write Protection - 5 Additional General Purpose Inputs for platform design flexibility - Synchronized with 33 MHz PCI clock
TSOP40 (N) 10 x 20mm
Figure 1. Logic Diagram (LPC Interface)
VCC VPP 4 ID0-ID3 5 GPI0GPI4 LFRAME CLK IC RP INIT M50LPW116 WP TBL 4 LAD0LAD3
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BYTE PROGRAMMING TIME - Single Byte Mode: 10s (typical) - Quadruple Byte Mode: 2.5s (typical)
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50 MEMORY BLOCKS - 1 Boot Block - 18 Parameter and 31 Main Blocks
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PROGRAM/ERASE CONTROLLER - Embedded Byte Program and Block/Chip Erase algorithms - Status Register Bits
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PROGRAM and ERASE SUSPEND ELECTRONIC SIGNATURE - Manufacturer Code: 20h - Device Code: 30h
VSS
AI05466
February 2003
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
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Figure 2. Logic Diagram (A/A Mux Interface) DESCRIPTION The M50LPW116 is a 16 Mbit (2Mb x8) nonvolatile memory that can be read, erased and reprogrammed. These operations can be performed using a single low voltage (3.0 to 3.6V) supply. For fast programming, and fast erasing, an optional 12V power supply can be used to reduce the programming and the erasing times. The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old data is erased. Blocks can be protected individually (except Blocks 15 to 0, which have global protection) to prevent accidental Program or Erase commands from modifying the memory. Program and Erase commands are written to the Command Interface of the memory. An on-chip Program/Erase Controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. The end of a program or erase operation can be detected and any error conditions identified. The command set required to control the memory is consistent with JEDEC standards. The M50LPW116 features an asymmetrical block architecture. It has an array of 50 blocks: 1 Boot Block of 16KBytes, 2 Parameter Blocks of
VCC VPP 11 A0-A10 8 DQ0-DQ7
RC IC G W RP M50LPW116 RB
VSS
AI05468
Figure 3. TSOP Connections
NC IC (VIH) NC NC NC NC A10 NC RC VCC VPP RP NC NC A9 A8 A7 A6 A5 A4
NC IC (VIL) NC NC NC NC GPI4 NC CLK VCC VPP RP NC NC GPI3 GPI2 GPI1 GPI0 WP TBL
1
40
10 31 M50LPW116 11 30
20
21
VSS VCC LFRAME INIT RFU RFU RFU RFU RFU VCC VSS VSS LAD3 LAD2 LAD1 LAD0 ID0 ID1 ID2 ID3
VSS VCC W G RB DQ7 DQ6 DQ5 DQ4 VCC VSS VSS DQ3 DQ2 DQ1 DQ0 A0 A1 A2 A3
A/A Mux
A/A Mux
AI05467
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8KBytes, 1 Main Block of 32KBytes, 30 Main Blocks of 64KBytes and 16 Parameter Blocks of 4KBytes. Two different bus interfaces are supported by the memory. The primary interface is the Low Pin Count (or LPC) Standard Interface. This has been designed to remove the need for the ISA bus in current PC Chipsets; the M50LPW116 acts as the PC BIOS on the Low Pin Count bus for these PC Chipsets. The secondary interface, the Address/Address Multiplexed (or A/A Mux) Interface, is designed to be compatible with current Flash Programmers for production line programming prior to fitting to a PC Motherboard. The memory is offered in TSOP40 (10 x 20mm) package and it is supplied with all the bits erased (set to '1'). SIGNAL DESCRIPTIONS There are two different bus interfaces available on this part. The active interface is selected before power-up or during Reset using the Interface Configuration Pin, IC. The signals for each interface are discussed in the Low Pin Count (LPC) Signal Descriptions section and the Address/Address Multiplexed (A/A Mux) Signal Descriptions section below. The supply signals are discussed in the Supply Signal Descriptions section below. Low Pin Count (LPC) Signal Descriptions For the Low Pin Count (LPC) Interface see Figure 1, Logic Diagram (LPC Interface), and Table 1, Signal Names (LPC Interface). The LPC address sequence is 32 bits long. The M50LPW116 responds to addresses mapped to the top of the 4 GByte memory space, from FFFF FFFFh. Address bits A31-A26 must be set to 1. For A25-A23 and A21, refer to Table 2. A22 is set to 1 for array access, and to 0 for register access. A20-A0 are for array addresses. Input/Output Communications (LAD0-LAD3). All Input and Output Communication with the memory take place on these pins. Addresses and Data for Bus Read and Bus Write operations are encoded on these pins. Input Communication Frame (LFRAME). The Input Communication Frame (LFRAME) signals the start of a bus operation. When Input Communication Frame is Low, VIL, on the rising edge of the Clock a new bus operation is initiated. If Input Communication Frame is Low, VIL, during a bus operation then the operation is aborted. When Input Communication Frame is High, VIH, the current bus operation is proceeding or the bus is idle. Table 1. Signal Names (LPC Interface)
LAD0-LAD3 LFRAME ID0-ID3 GPI0-GPI4 IC RP INIT CLK TBL WP RFU VCC VPP VSS NC Input/Output Communications Input Communication Frame Identification Inputs General Purpose Inputs Interface Configuration Interface Reset CPU Reset Clock Top Block Lock Write Protect Reserved for Future Use. Leave disconnected. Supply Voltage Optional Supply Voltage for Fast Program and Fast Erase Operations Ground Not Connected Internally
Identification Inputs (ID0-ID3). The Identification Inputs (ID0-ID3) allow to address up to 16 memories on a bus. The value on addresses A21,A23-A25 is compared to the hardware strapping on the ID0-ID3 pins to select which memory is being addressed. For an address bit to be `1' the correspondent ID pin can be left floating or driven Low, VIL; an internal pull-down resistor is included with a value of R IL. For an address bit to be `0' the correspondent ID pin must be driven High, V IH; there will be a leakage current of ILI2 through each pin when pulled to V IH; see Table 20. By convention the boot memory must have ID0ID3 pins left floating or driven Low, V IL and a `1' value on A21,A23-A25 and all additional memories take sequential ID0-ID3 configuration, as shown in Table 2. General Purpose Inputs (GPI0-GPI4). The General Purpose Inputs can be used as digital inputs for the CPU to read. The General Purpose Input Register holds the values on these pins. The pins must have stable data from before the start of the cycle that reads the General Purpose Input Register until after the cycle is complete. These pins must not be left to float, they should be driven Low, V IL, or High, V IH.
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Table 2. Memory Identification Input Configuration
Memory Number 1 (Boot) 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 ID3 VIL or floating VIL or floating VIL or floating VIL or floating VIL or floating VIL or floating VIL or floating VIL or floating VIH VIH VIH VIH VIH VIH VIH VIH ID2 VIL or floating VIL or floating VIL or floating VIL or floating VIH VIH VIH VIH VIL or floating VIL or floating VIL or floating VIL or floating VIH VIH VIH VIH ID1 VIL or floating VIL or floating VIH VIH VIL or floating VIL or floating VIH VIH VIL or floating VIL or floating VIH VIH VIL or floating VIL or floating VIH VIH ID0 VIL or floating VIH VIL or floating VIH VIL or floating VIH VIL or floating VIH VIL or floating VIH VIL or floating VIH VIL or floating VIH VIL or floating VIH A25 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 A24 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 A23 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 A21 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
Interface Configuration (IC). The Interface Configuration input selects whether the Low Pin Count (LPC) or the Address/Address Multiplexed (A/A Mux) Interface is used. The chosen interface must be selected before power-up or during a Reset and, thereafter, cannot be changed. The state of the Interface Configuration, IC, should not be changed during operation. To select the Low Pin Count (LPC) Interface the Interface Configuration pin should be left to float or driven Low, VIL; to select the Address/Address Multiplexed (A/A Mux) Interface the pin should be driven High, VIH. An internal pull-down resistor is included with a value of RIL; there will be a leakage current of ILI2 through each pin when pulled to VIH; see Table 20. Interface Reset (RP). The Interface Reset (RP) input is used to reset the memory. When Interface Reset (RP) is set Low, VIL, the memory is in Reset mode: the outputs are put to high impedance and the current consumption is minimized. When RP is set High, V IH, the memory is in normal operation. After exiting Reset mode, the memory enters Read mode.
CPU Reset (INIT). The CPU Reset, INIT, pin is used to Reset the memory when the CPU is reset. It behaves identically to Interface Reset, RP, and the internal Reset line is the logical OR (electrical AND) of RP and INIT. Clock (CLK). The Clock, CLK, input is used to clock the signals in and out of the Input/Output Communication Pins, LAD0-LAD3. The Clock conforms to the PCI specification. Top Block Lock (TBL). The Top Block Lock input is used to prevent the Top Block (Block 49) from being changed. When Top Block Lock, TBL, is set Low, VIL, Program and Block Erase operations in the Top Block have no effect, regardless of the state of the Lock Register. When Top Block Lock, TBL, is set High, V IH, the protection of the Block is determined by the Lock Register. The state of Top Block Lock, TBL, does not affect the protection of the other Blocks (Blocks 0 to 48). Top Block Lock, TBL, must be set prior to a Program or Block Erase operation is initiated and must not be changed until the operation completes or unpredictable results may occur. Care should be taken to avoid unpredictable behavior by changing TBL during Program or Erase Suspend.
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Table 3. Signal Names (A/A Mux Interface)
IC A0-A10 DQ0-DQ7 G W RC RB RP VCC VPP VSS NC Interface Configuration Address Inputs Data Inputs/Outputs Output Enable Write Enable Row/Column Address Select Ready/Busy Output Interface Reset Supply Voltage Optional Supply Voltage for Fast Program and Fast Erase Operations Ground Not Connected Internally
Write Protect (WP). The Write Protect input is used to prevent the Blocks 0 to 48 from being changed. When Write Protect, WP, is set Low, VIL, Program and Block Erase operations in the Blocks 0 to 48 have no effect, regardless of the state of the Lock Register. When Write Protect, WP, is set High, VIH, the protection of the Block is determined by the Lock Register. The state of Write Protect, WP, does not affect the protection of the Top Block (Block 49). Write Protect, WP, must be set prior to a Program or Block Erase operation is initiated and must not be changed until the operation completes or unpredictable results may occur. Care should be taken to avoid unpredictable behavior by changing WP during Program or Erase Suspend. Reserved for Future Use (RFU). These pins do not have assigned functions in this revision of the part. They must be left disconnected. Address/Address Multiplexed (A/A Mux) Signal Descriptions For the Address/Address Multiplexed (A/A Mux) Interface see Figure 2, Logic Diagram (A/A Mux Interface), and Table 3, Signal Names (A/A Mux Interface). Address Inputs (A0-A10). The Address Inputs are used to set the Row Address bits (A0-A10) and the Column Address bits (A11-A20). They are latched during any bus operation by the Row/Column Address Select input, RC.
Data Inputs/Outputs (DQ0-DQ7). The Data Inputs/Outputs hold the data that is written to or read from the memory. They output the data stored at the selected address during a Bus Read operation. During Bus Write operations they represent the commands sent to the Command Interface of the internal state machine. The Data Inputs/Outputs, DQ0-DQ7, are latched during a Bus Write operation. Output Enable (G). The Output Enable, G, controls the Bus Read operation of the memory. Write Enable (W). The Write Enable, W, controls the Bus Write operation of the memory's Command Interface. Row/Column Address Select (RC). The Row/ Column Address Select input selects whether the Address Inputs should be latched into the Row Address bits (A0-A10) or the Column Address bits (A11-A20). The Row Address bits are latched on the falling edge of RC whereas the Column Address bits are latched on the rising edge. Ready/Busy Output (RB). The Ready/Busy pin gives the status of the memory's Program/Erase Controller. When Ready/Busy is Low, VOL, the memory is busy with a Program or Erase operation and it will not accept any additional Program or Erase command except the Program/Erase Suspend command. When Ready/Busy is High, VOH, the memory is ready for any Read, Program or Erase operation. Supply Signal Descriptions The Supply Signals are the same for both interfaces. VCC Supply Voltage. The VCC Supply Voltage supplies the power for all operations (Read, Program, Erase etc.). The Command Interface is disabled when the V CC Supply Voltage is less than the Lockout Voltage, VLKO. This prevents Bus Write operations from accidentally damaging the data during power up, power down and power surges. If the Program/ Erase Controller is programming or erasing during this time then the operation aborts and the memory contents being altered will be invalid. After VCC becomes valid the Command Interface is reset to Read mode. A 0.1F capacitor should be connected between the VCC Supply Voltage pins and the VSS Ground pin to decouple the current surges from the power supply. Both V CC Supply Voltage pins must be connected to the power supply. The PCB track widths must be sufficient to carry the currents required during program and erase operations.
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Table 4. Absolute Maximum Ratings (1)
Symbol TA Ambient Operating Temperature (Temperature Range Option 5) TBIAS TSTG VIO (2) VCC VPP Temperature Under Bias Storage Temperature Input or Output Voltage Supply Voltage Program Voltage -20 to 85 -50 to 125 -65 to 150 -0.6 to VCC + 0.6 -0.6 to 4 -0.6 to 13 C C C V V V Parameter Ambient Operating Temperature (Temperature Range Option 1) Value 0 to 70 Unit C
Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. 2. Minimum Voltage may undershoot to -2V and for less than 20ns during transitions. Maximum Voltage may overshoot to VCC +2V and for less than 20ns during transitions.
VPP Optional Supply Voltage. The VPP Optional Supply Voltage pin is used to select the Fast Program (see the Quadruple Byte Program Command description) and Fast Erase options of the memory and to protect the memory. When VPP < VPPLK Program and Erase operations cannot be performed and an error is reported in the Status Register if an attempt to change the memory contents is made. When VPP = VCC Program and Erase operations take place as normal. When V PP = VPPH Fast Program operations (using the Quadruple Byte Program command, 30h, from Table 11) and Fast Erase operations are used. Any other voltage input to VPP will result in undefined behavior and should not be used. VPP should not be set to VPPH for more than 80 hours during the life of the memory. VSS Ground. VSS is the reference for all the voltage measurements. BUS OPERATIONS The two interfaces have similar bus operations but the signals and timings are completely different. The Low Pin Count (LPC) Interface is the usual interface and all of the functionality of the part is available through this interface. Only a subset of functions are available through the Address/ Address Multiplexed (A/A Mux) Interface. Follow the section Low Pin Count (LPC) Bus Operations below and the section Address/ Address Multiplexed (A/A Mux) Interface Bus Operations below for a description of the bus operations on each interface.
Low Pin Count (LPC) Bus Operations The Low Pin Count (LPC) Interface consists of four data signals (LAD0-LAD3), one control line (LFRAME) and a clock (CLK). In addition protection against accidental or malicious data corruption can be achieved using two further signals (TBL and WP). Finally two reset signals (RP and INIT) are available to put the memory into a known state. The data signals, control signal and clock are designed to be compatible with PCI electrical specifications. The interface operates with clock speeds up to 33MHz. The following operations can be performed using the appropriate bus cycles: Bus Read, Bus Write, Standby, Reset and Block Protection. Bus Read. Bus Read operations read from the memory cells, specific registers in the Command Interface or Low Pin Count Registers. A valid Bus Read operation starts when Input Communication Frame, LFRAME, is Low, V IL, as Clock rises and the correct Start cycle is on LAD0-LAD3. On the following clock cycles the Host will send the Cycle Type + Dir, Address and other control bits on LAD0-LAD3. The memory responds by outputting Sync data until the wait-states have elapsed followed by Data0-Data3 and Data4-Data7. See Table 6, and to Figure 4, for a description of the Field definitions for each clock cycle of the transfer. See Table 22, and Figure 9, for details on the timings of the signals. Bus Write. Bus Write operations write to the Command Interface or Low Pin Count Registers. A valid Bus Write operation starts when Input Communication Frame, LFRAME, is Low, VIL, as Clock rises and the correct Start cycle is on LAD0-
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Table 5. Block Addresses
Size (Kbytes) 16 8 8 32 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 Address Range 1FC000h-1FFFFFh 1FA000h-1FBFFFh 1F8000h-1F9FFFh 1F0000h-1F7FFFh 1E0000h-1EFFFFh 1D0000h-1DFFFFh 1C0000h-1CFFFFh 1B0000h-1BFFFFh 1A0000h-1AFFFFh 190000h-19FFFFh 180000h-18FFFFh 170000h-17FFFFh 160000h-16FFFFh 150000h-15FFFFh 140000h-14FFFFh 130000h-13FFFFh 120000h-12FFFFh 110000h-11FFFFh 100000h-10FFFFh 0F0000h-0FFFFFh 0E0000h-0EFFFFh 0D0000h-0DFFFFh 0C0000h-0CFFFFh 0B0000h-0BFFFFh Block Number 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 Block Type Boot (Top) Parameter Parameter Main Main Main Main Main Main Main Main Main Main Main Main Main Main Main Main Main Main Main Main Main 64 64 64 64 64 64 64 64 64 64 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 0A0000h-0AFFFFh 090000h-09FFFFh 080000h-08FFFFh 070000h-07FFFFh 060000h-06FFFFh 050000h-05FFFFh 040000h-04FFFFh 030000h-03FFFFh 020000h-02FFFFh 010000h-01FFFFh 00F000h-00FFFFh 00E000h-00EFFFh 00D000h-00DFFFh 00C000h-00CFFFh 00B000h-00BFFFh 00A000h-00AFFFh 009000h-009FFFh 008000h-008FFFh 007000h-007FFFh 006000h-006FFFh 005000h-005FFFh 004000h-004FFFh 003000h-003FFFh 002000h-002FFFh 001000h-001FFFh 000000h-000FFFh 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Main Main Main Main Main Main Main Main Main Main Parameter Parameter Parameter Parameter Parameter Parameter Parameter Parameter Parameter Parameter Parameter Parameter Parameter Parameter Parameter Parameter
Note: For A21 and A23, refer to Table 2. A22 is set to 1.
LAD3. On the following Clock cycles the Host will send the Cycle Type + Dir, Address, other control bits, Data0-Data3 and Data4-Data7 on LAD0LAD3. The memory outputs Sync data until the wait-states have elapsed. See Table 7, and to Figure 5, for a description of the Field definitions for each clock cycle of the transfer. See Table 22, and Figure 9, for details on the timings of the signals. Bus Abort. The Bus Abort operation can be used to immediately abort the current bus operation. A Bus Abort occurs when LFRAME is driven Low, VIL, during the bus operation; the memory will tristate the Input/Output Communication pins, LAD0-LAD3.
Note that, during a Bus Write operation, the Command Interface starts executing the command as soon as the data is fully received; a Bus Abort during the final TAR cycles is not guaranteed to abort the command; the bus, however, will be released immediately. Standby. When LFRAME is High, VIH, the memory is put into Standby mode where LAD0LAD3 are put into a high-impedance state and the Supply Current is reduced to the Standby level, ICC1. Reset. During Reset mode all internal circuits are switched off, the memory is deselected and the outputs are put in high-impedance. The memory is in Reset mode when Interface Reset, RP, or CPU Reset, INIT, is Low, VIL. RP or INIT must be held
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Table 6. LPC Bus Read Field Definitions
Clock Cycle Number Clock Cycle Count 1 Field LAD0LAD3 Memory I/O Description On the rising edge of CLK with LFRAME Low, the contents of LAD0-LAD3 must be 0000b to indicate the start of a LPC cycle. Indicates the type of cycle and selects 1-byte reading. Bits 3:2 must be 01b. Bit 1 indicates the direction of transfer: 0b for read. Bit 0 is reset to 0. A 32-bit address phase is transferred starting with the most significant nibble first. A26-A31 must be set to 1. A22 = 1 for Array, A22 = 0 for registers access. For A21, A23A25 values, refers to Table 2. The host drives LAD0-LAD3 to 1111b to indicate a turnaround cycle. The LPC Flash Memory takes control of LAD0-LAD3 during this cycle. The LPC Flash Memory drives LAD0-LAD3 to 0101b (short wait-sync) for two clock cycles, indicating that the data is not yet available. Two wait-states are always included. The LPC Flash Memory drives LAD0-LAD3 to 0000b, indicating that data will be available during the next clock cycle. Data transfer is two CLK cycles, starting with the least significant nibble. The LPC Flash Memory drives LAD0-LAD3 to 1111b to indicate a turnaround cycle. The LPC Flash Memory floats its outputs, the host takes control of LAD0-LAD3.
1
START
0000b
I
2
1
CYCTYPE + DIR
0100b
I
3-10
8
ADDR
XXXX
I
11 12
1 1
TAR TAR
1111b 1111b (float)
I O
13-14
2
WSYNC
0101b
O
15
1
RSYNC
0000b
O
16-17 18 19
2 1 1
DATA TAR TAR
XXXX 1111b 1111b (float)
O O N/A
Figure 4. LPC Bus Read Waveforms
CLK
LFRAME
LAD0-LAD3 Number of clock cycles
START 1
CYCTYPE + DIR 1
ADDR 8
TAR 2
SYNC 3
DATA 2
TAR 2 AI04429
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Table 7. LPC Bus Write Field Definitions
Clock Cycle Number 1 Clock Cycle Count 1 Field LAD0LAD3 Memory I/O Description On the rising edge of CLK with LFRAME Low, the contents of LAD0-LAD3 must be 0000b to indicate the start of a LPC cycle. Indicates the type of cycle. Bits 3:2 must be 01b. Bit 1 indicates the direction of transfer: 1b for write. Bit 0 is don't care (X). A 32-bit address phase is transferred starting with the most significant nibble first. A26-A31 must be set to 1. A22 = 1 for Array, A22 = 0 for registers access. For A21, A23-A25 values, refers to Table 2. Data transfer is two cycles, starting with the least significant nibble. The host drives LAD0-LAD3 to 1111b to indicate a turnaround cycle. The LPC Flash Memory takes control of LAD0-LAD3 during this cycle. The LPC Flash Memory drives LAD0-LAD3 to 0000b, indicating it has received data or a command. The LPC Flash Memory drives LAD0-LAD3 to 1111b, indicating a turnaround cycle. The LPC Flash Memory floats its outputs and the host takes control of LAD0-LAD3.
START CYCTY PE + DIR
0000b
I
2
1
011Xb
I
3-10
8
ADDR
XXXX
I
11-12 13 14 15 16 17
2 1 1 1 1 1
DATA TAR TAR SYNC TAR TAR
XXXX 1111b 1111b (float) 0000b 1111b 1111b (float)
I I O O O N/A
Figure 5. LPC Bus Write Waveforms
CLK
LFRAME
LAD0-LAD3 Number of clock cycles
START 1
CYCTYPE + DIR 1
ADDR 8
DATA 2
TAR 2
SYNC 1
TAR 2 AI04430
Low, V IL, for tPLPH. The memory resets to Read mode upon return from Reset mode and the Lock Registers return to their default states regardless of their state before Reset, see Table 15. If RP or INIT goes Low, VIL, during a Program or Erase operation, the operation is aborted and the memory cells affected no longer contain valid data; the memory can take up to tPLRH to abort a Program or Erase operation. Block Protection. Block Protection can be forced using the signals Top Block Lock, TBL, and
Write Protect, WP, regardless of the state of the Lock Registers. Address/Address Multiplexed (A/A Mux) Bus Operations The Address/Address Multiplexed (A/A Mux) Interface has a more traditional style interface. The signals consist of a multiplexed address signals (A0-A10), data signals, (DQ0-DQ7) and three control signals (RC, G, W). An additional signal, RP, can be used to reset the memory.
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Table 8. A/A Mux Bus Operations
Operation Bus Read Bus Write Output Disable Reset G VIL VIH VIH VIL or VIH W VIH VIL VIH VIL or VIH RP VIH VIH VIH VIL VPP Don't Care VCC or VPPH Don't Care Don't Care DQ7-DQ0 Data Output Data Input Hi-Z Hi-Z
Table 9. Manufacturer and Device Codes
Operation Manufacturer Code Device Code G VIL VIL W VIH VIH RP VIH VIH A20-A1 VIL VIL A0 VIL VIH DQ7-DQ0 20h 30h
The Address/Address Multiplexed (A/A Mux) Interface is included for use by Flash Programming equipment for faster factory programming. Only a subset of the features available to the Low Pin Count (LPC) Interface are available; these include all the Commands but exclude the Security features and other registers. The following operations can be performed using the appropriate bus cycles: Bus Read, Bus Write, Output Disable and Reset. When the Address/Address Multiplexed (A/A Mux) Interface is selected all the blocks are unprotected. It is not possible to protect any blocks through this interface. Bus Read. Bus Read operations are used to output the contents of the Memory Array, the Electronic Signature and the Status Register. A valid Bus Read operation begins by latching the Row Address and Column Address signals into the memory using the Address Inputs, A0-A10, and the Row/Column Address Select RC. Then Write Enable (W) and Interface Reset (RP) must be High, V IH, and Output Enable, G, Low, VIL, in order to perform a Bus Read operation. The Data Inputs/Outputs will output the value, see Figure 11, A/A Mux Interface Read AC Waveforms, and Table 24, for details of when the output becomes valid. Bus Write. Bus Write operations write to the Command Interface. A valid Bus Write operation begins by latching the Row Address and Column Address signals into the memory using the Address Inputs, A0-A10, and the Row/Column Address Select RC. The data should be set up on the Data Inputs/Outputs; Output Enable, G, and Interface Reset, RP, must be High, VIH and Write Enable, W, must be Low, V IL. The Data Inputs/ Outputs are latched on the rising edge of Write Enable, W. See Figure 12, and Table 25, for details of the timing requirements.
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Output Disable. The data outputs are high-impedance when the Output Enable, G, is at VIH. Reset. During Reset mode all internal circuits are switched off, the memory is deselected and the outputs are put in high-impedance. The memory is in Reset mode when RP is Low, VIL. RP must be held Low, VIL for tPLPH. If RP is goes Low, VIL, during a Program or Erase operation, the operation is aborted and the memory cells affected no longer contain valid data; the memory can take up to tPLRH to abort a Program or Erase operation. COMMAND INTERFACE All Bus Write operations to the memory are interpreted by the Command Interface. Commands consist of one or more sequential Bus Write operations. After power-up or a Reset operation the memory enters Read mode. The commands are summarized in Table 11, Commands. Refer to Table 11 in conjunction with the text descriptions below. Read Memory Array Command. The Read Memory Array command returns the memory to its Read mode where it behaves like a ROM or EPROM. One Bus Write cycle is required to issue the Read Memory Array command and return the memory to Read mode. Once the command is issued the memory remains in Read mode until another command is issued. From Read mode Bus Read operations will access the memory array. While the Program/Erase Controller is executing a Program or Erase operation the memory will not accept the Read Memory Array command until the operation completes. Read Status Register Command. The Read Status Register command is used to read the Status Register. One Bus Write cycle is required to issue the Read Status Register command. Once the
M50LPW116
command is issued subsequent Bus Read operations read the Status Register until another command is issued. See the section on the Status Register for details on the definitions of the Status Register bits. Read Electronic Signature Command. The Read Electronic Signature command is used to read the Manufacturer Code and the Device Code. One Bus Write cycle is required to issue the Read Electronic Signature command. Once the command is issued subsequent Bus Read operations read the Manufacturer Code or the Device Code until another command is issued. After the Read Electronic Signature Command is issued the Manufacturer Code and Device Code can be read using Bus Read operations using the addresses in Table 10. Program Command. The Program command can be used to program a value to one address in the memory array at a time. Two Bus Write operations are required to issue the command; the second Bus Write cycle latches the address and data in the internal state machine and starts the Program/Erase Controller. Once the command is issued subsequent Bus Read operations read the Status Register. See the section on the Status Register for details on the definitions of the Status Register bits. If the address falls in a protected block then the Program operation will abort, the data in the memory array will not be changed and the Status Register will output the error. During the Program operation the memory will only accept the Read Status Register command and the Program/Erase Suspend command. All other commands will be ignored. Typical Program times are given in Table 12. Note that the Program command cannot change a bit set at `0' back to `1' and attempting to do so will not cause any modification on its value. One of the Erase commands must be used to set all of the bits in the block to `1'. See Figure 13, for a suggested flowchart on using the Program command. Quadruple Byte Program Command (A/A Mux Mode). The Quadruple Byte Program Command can be used to program four adjacent bytes in the memory array at a time. The four bytes must differ only for the addresses A0 and A1. Programming should not be attempted when V PP is not at V PPH. Five Bus Write operations are required to issue the command. The second, the third and the fourth Bus Write cycle latches respectively the address and data of the first, the second and the third byte in the internal state machine. The fifth Bus Write cycle latches the address and data of the fourth byte in the internal state machine and starts the Table 10. Read Electronic Signature
Code Manufacturer Code Device Code Address 000000h 000001h Data 20h 30h
Program/Erase Controller. Once the command is issued subsequent Bus Read operations read the Status Register. See the section on the Status Register for details on the definitions of the Status Register bits. During the Quadruple Byte Program operation the memory will only accept the Read Status register command and the Program/Erase Suspend command. All other commands will be ignored. Typical Quadruple Byte Program times are given in Table 12. Note that the Quadruple Byte Program command cannot change a bit set to `0' back to `1' and attempting to do so will not cause any modification on its value. One of the Erase commands must be used to set all of the bits in the block to `1'. See Figure 14, for a suggested flowchart on using the Quadruple Byte Program command. Chip Erase Command. The Chip Erase Command can be only used in A/A Mux mode to erase the entire chip at a time. Erasing should not be attempted when VPP is not at VPPH. The operation can also be executed if V PP is below VPPH, but result could be uncertain. Two Bus Write operations are required to issue the command and start the Program/Erase Controller. Once the command is issued subsequent Bus Read operations read the Status Register. See the section on the Status Register for details on the definitions of the Status Register bits. During the Chip Erase operation the memory will only accept the Read Status Register command. All other commands will be ignored. Typical Chip Erase times are given in Table 12. The Chip Erase command sets all of the bits in the memory to `1'. See Figure 16, Chip Erase Flowchart and Pseudo Code (A/A Mux Interface Only), for a suggested flowchart on using the Chip Erase command. Block Erase Command. The Block Erase command can be used to erase a block. Two Bus Write operations are required to issue the command; the second Bus Write cycle latches the block address in the internal state machine and starts the Program/Erase Controller. Once the command is issued subsequent Bus Read operations read the Status Register. See the section on the Status Register for details on the definitions of the Status Register bits. If the block is protected then the Block Erase operation will abort, the data in the block will not be
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Table 11. Commands
Cycles Bus Write Operations 1st Addr X X X X X X X X X X X X X X X X X Data FFh 70h 90h 98h 40h 10h 30h 80h 20h 50h B0h D0h 00h 01h 60h 2Fh C0h PA PA A1 X BA PD PD PD 10h D0h A2 PD A3 PD A4 PD 2nd Addr Data 3rd Addr Data 4th Addr Data 5th Addr Data Command
Read Memory Array Read Status Register Read Electronic Signature
1 1 1 1 2
Program 2 Quadruple Byte Program (A/A Mux Mode) Chip Erase Block Erase Clear Status Register Program/Erase Suspend Program/Erase Resume 5 2 2 1 1 1 1 1 Invalid/Reserved 1 1 1
Note: X Don't Care, PA Program Address, PD Program Data, A1,2,3,4 Consecutive Addresses, BA Any address in the Block. Read Memory Array. After a Read Memory Array command, read the memory as normal until another command is issued. Read Status Register. After a Read Status Register command, read the Status Register as normal until another command is issued. Read Electronic Signature. After a Read Electronic Signature command, read Manufacturer Code, Device Code until another command is issued. Block Erase, Program. After these commands read the Status Register until the command completes and another command is issued. Quadruple Byte Program (A/A Mux Mode). Addresses A 1, A2, A3 and A4 must be consecutive addresses differing only for address bit A0 and A1. After this command, the user should repeatedly read the Status Register until the command has completed, at which point another command can be issued. Chip Erase. This command is only valid in A/A Mux mode. After this command read the Status Register until the command completes and another command is issued. Clear Status Register. After the Clear Status Register command bits 1, 3, 4 and 5 in the Status Register are reset to `0'. Program/Erase Suspend. After the Program/Erase Suspend command has been accepted, issue Read Memory Array, Read Status Register, Program (during Erase suspend) and Program/Erase resume commands. Program/Erase Resume. After the Program/Erase Resume command the suspended Program/Erase operation resumes, read the Status Register until the Program/Erase Controller completes and the memory returns to Read Mode. Invalid/Reserved. Do not use Invalid or Reserved commands.
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Table 12. Program and Erase Times (TA = 0 to 70C or -20 to 85C; VCC = 3.0 to 3.6V)
Parameter Byte Program Quadruple Byte Program Chip Erase Block Program (64 Kbytes) VPP = VCC VPP = 12V 5% Block Erase (64 Kbytes) VPP = VCC Program/Erase Suspend to Program pause (3) Program/Erase Suspend to Block Erase pause (3)
Note: 1. 2. 3. 4. TA = 25C, VCC = 3.3V This time is obtained executing the Quadruple Byte Program Command. Sampled only, not 100% tested. Time to program four bytes.
Interface
Test Condition
Min
Typ (1) 10
Max 200 200
Unit s s sec
A/A Mux A/A Mux A/A Mux
VPP = 12V 5% VPP = 12V 5% VPP = 12V 5%
10 (4) 18 0.1 (2) 0.4 0.75 1
5 5 8 10 5 30
sec sec sec sec s s
changed and the Status Register will output the error. During the Block Erase operation the memory will only accept the Read Status Register command and the Program/Erase Suspend command. All other commands will be ignored. Typical Block Erase times are given in Table 12. The Block Erase command sets all of the bits in the block to `1'. All previous data in the block is lost. See Figure 17, Block Erase Flowchart and Pseudo Code, for a suggested flowchart on using the Erase command. Clear Status Register Command. The Clear Status Register command can be used to reset bits 1, 3, 4 and 5 in the Status Register to `0'. One Bus Write is required to issue the Clear Status Register command. Once the command is issued the memory returns to its previous mode, subsequent Bus Read operations continue to output the same data. The bits in the Status Register are sticky and do not automatically return to `0' when a new Program or Erase command is issued. If an error occurs then it is essential to clear any error bits in the Status Register by issuing the Clear Status Register command before attempting a new Program or Erase command. Program/Erase Suspend Command. The Program/Erase Suspend command can be used to pause a Program or Block Erase operation. One Bus Write cycle is required to issue the Program/ Erase Suspend command and pause the Program/Erase Controller. Once the command is issued it is necessary to poll the Program/Erase
Controller Status bit to find out when the Program/ Erase Controller has paused; no other commands will be accepted until the Program/Erase Controller has paused. After the Program/Erase Controller has paused, the memory will continue to output the Status Register until another command is issued. During the polling period between issuing the Program/Erase Suspend command and the Program/Erase Controller pausing it is possible for the operation to complete. Once Program/Erase Controller Status bit indicates that the Program/ Erase Controller is no longer active, the Program Suspend Status bit or the Erase Suspend Status bit can be used to determine if the operation has completed or is suspended. For timing on the delay between issuing the Program/Erase Suspend command and the Program/Erase Controller pausing see Table 12. During Program/Erase Suspend the Read Memory Array, Read Status Register, Read Electronic Signature and Program/Erase Resume commands will be accepted by the Command Interface. Additionally, if the suspended operation was Block Erase then the Program command will also be accepted; only the blocks not being erased may be read or programmed correctly. See Figure 15, Program Suspend and Resume Flowchart and Pseudo Code, and Figure 18, Erase Suspend & Resume Flowchart and Pseudo Code, for suggested flowcharts on using the Program/Erase Suspend command. Program/Erase Resume Command. The Program/Erase Resume command can be used to restart the Program/Erase Controller after a
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Table 13. Status Register Bits
Operation Program active Program suspended Program completed successfully Program failure due to VPP Error Program failure due to Block Protection (LPC Interface only) Program failure due to cell failure Erase active Block Erase suspended Erase completed successfully Erase failure due to VPP Error Block Erase failure due to Block Protection (LPC Interface only) Erase failure due to failed cell(s) Sequence command error Bit 7 `0' `1 `1' `1' `1' `1' `0' `1' `1' `1' `1' `1' `1' Bit 6 X(1) X(1) X(1) X(1) X(1) X(1) `0' `1' `0' `0' `0' `0' `0' Bit 5 `0' `0' `0' `0' `0' `0' `0' `0' `0' `0' `0' `1' `1' Bit 4 `0' `0' `0' `0' `0' `1' `0' `0' `0' `0' `0' `0' `1' Bit 3 `0' `0' `0' `1' `0' `0' `0' `0' `0' `1' `0' `0' `0' Bit 2 `0' `1' `0' `0' `0' `0' `0' `0' `0' `0' `0' `0' `0' Bit 1 `0' `0' `0' `0' `1' `0' `0' `0' `0' `0' `1' `0' `0'
Note: 1. For Program operations during Erase Suspend Bit 6 is `1', otherwise Bit 6 is `0'.
Program/Erase Suspend has paused it. One Bus Write cycle is required to issue the Program/Erase Resume command. Once the command is issued subsequent Bus Read operations read the Status Register. STATUS REGISTER The Status Register provides information on the current or previous Program or Erase operation. Different bits in the Status Register convey different information and errors on the operation. To read the Status Register the Read Status Register command can be issued. The Status Register is automatically read after Program, Erase and Program/Erase Resume commands are issued. The Status Register can be read from any address. The Status Register bits are summarized in Table 13, Status Register Bits. Refer to Table 13 in conjunction with the text descriptions below. Program/Erase Controller Status (Bit 7). The Program/Erase Controller Status bit indicates whether the Program/Erase Controller is active or inactive. When the Program/Erase Controller Status bit is `0', the Program/Erase Controller is active; when the bit is `1', the Program/Erase Controller is inactive. The Program/Erase Controller Status is `0' immediately after a Program/Erase Suspend command is issued until the Program/Erase Controller paus14/36
es. After the Program/Erase Controller pauses the bit is `1'. During Program and Erase operation the Program/Erase Controller Status bit can be polled to find the end of the operation. The other bits in the Status Register should not be tested until the Program/Erase Controller completes the operation and the bit is `1'. After the Program/Erase Controller completes its operation the Erase Status, Program Status, VPP Status and Block Protection Status bits should be tested for errors. Erase Suspend Status (Bit 6). The Erase Suspend Status bit indicates that a Block Erase operation has been suspended and is waiting to be resumed. The Erase Suspend Status should only be considered valid when the Program/Erase Controller Status bit is `1' (Program/Erase Controller inactive); after a Program/Erase Suspend command is issued the memory may still complete the operation rather than entering the Suspend mode. When the Erase Suspend Status bit is `0' the Program/Erase Controller is active or has completed its operation; when the bit is `1' a Program/Erase Suspend command has been issued and the memory is waiting for a Program/Erase Resume command. When a Program/Erase Resume command is issued the Erase Suspend Status bit returns to `0'.
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Erase Status (Bit 5). The Erase Status bit can be used to identify if the memory has applied the maximum number of erase pulses to the block(s) and still failed to verify that the block(s) has erased correctly. The Erase Status bit should be read once the Program/Erase Controller Status bit is `1' (Program/Erase Controller inactive). When the Erase Status bit is `0' the memory has successfully verified that the block(s) has erased correctly; when the Erase Status bit is `1' the Program/Erase Controller has applied the maximum number of pulses to the block(s) and still failed to verify that the block(s) has erased correctly. Once the Erase Status bit is set to `1' it can only be reset to `0' by a Clear Status Register command or a hardware reset. If it is set to `1' it should be reset before a new Program or Erase command is issued, otherwise the new command will appear to fail. (When Bit 4 and Bit 5 are set to `1', a wrong command sequence has been attempted). Program Status (Bit 4). The Program Status bit can be used to identify if the memory has applied the maximum number of program pulses to the byte and still failed to verify that the byte has programmed correctly. The Program Status bit should be read once the Program/Erase Controller Status bit is `1' (Program/Erase Controller inactive). When the Program Status bit is `0' the memory has successfully verified that the byte has programmed correctly; when the Program Status bit is `1' the Program/Erase Controller has applied the maximum number of pulses to the byte and still failed to verify that the byte has programmed correctly. Once the Program Status bit is set to `1' it can only be reset to `0' by a Clear Status Register command or a hardware reset. If it is set to `1' it should be reset before a new Program or Erase command is issued, otherwise the new command will appear to fail. (When Bit 4 and Bit 5 are set to `1', a wrong command sequence has been attempted). VPP Status (Bit 3). The VPP Status bit can be used to identify an invalid voltage on the V PP pin during Program and Erase operations. The VPP pin is only sampled at the beginning of a Program or Erase operation. Indeterminate results can occur if VPP becomes invalid during a Program or Erase operation. When the VPP Status bit is `0' the voltage on the VPP pin was sampled at a valid voltage; when the VPP Status bit is `1' the VPP pin has a voltage that is below the V PP Lockout Voltage, VPPLK, the memory is protected; Program and Erase operation cannot be performed. (The VPP status bit is `1' if a Quadruple Byte Program command is issued and the V PP signal has a voltage less than VPPH applied to it.) Once the VPP Status bit set to `1' it can only be reset to `0' by a Clear Status Register command or a hardware reset. If it is set to `1' it should be reset before a new Program or Erase command is issued, otherwise the new command will appear to fail. Program Suspend Status (Bit 2). The Program Suspend Status bit indicates that a Program operation has been suspended and is waiting to be resumed. The Program Suspend Status should only be considered valid when the Program/Erase Controller Status bit is `1' (Program/Erase Controller inactive); after a Program/Erase Suspend command is issued the memory may still complete the operation rather than entering the Suspend mode. When the Program Suspend Status bit is `0' the Program/Erase Controller is active or has completed its operation; when the bit is `1' a Program/ Erase Suspend command has been issued and the memory is waiting for a Program/Erase Resume command. When a Program/Erase Resume command is issued the Program Suspend Status bit returns to `0'. Block Protection Status (Bit 1). The Block Protection Status bit can be used to identify if the Program or Block Erase operation has tried to modify the contents of a protected block. When the Block Protection Status bit is to `0' no Program or Block Erase operations have been attempted to protected blocks since the last Clear Status Register command or hardware reset; when the Block Protection Status bit is `1' a Program or Block Erase operation has been attempted on a protected block. Once it is set to `1' the Block Protection Status bit can only be reset to `0' by a Clear Status Register command or a hardware reset. If it is set to `1' it should be reset before a new Program or Block Erase command is issued, otherwise the new command will appear to fail. Using the A/A Mux Interface the Block Protection Status bit is always `0'. Reserved (Bit 0). Bit 0 of the Status Register is reserved. Its value should be masked. LOW PIN COUNT (LPC) INTERFACE CONFIGURATION REGISTERS When the Low Pin Count Interface is selected several additional registers can be accessed. These registers control the protection status of the Blocks and read the General Purpose Input pins. See Table 14 for an example of the Register Configuration map, valid for the boot memory, i.e. ID0-ID3 floating or driven LOW, VIL and A21, A23-A25 set to `1'.
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Table 14. Low Pin Count Register Configuration Map (1)
Mnemonic T_BLOCK_LK T_MINUS01_LK T_MINUS02_LK T_MINUS03_LK T_MINUS04_LK T_MINUS05_LK T_MINUS06_LK T_MINUS07_LK T_MINUS08_LK T_MINUS09_LK T_MINUS00_LK T_MINUS11_LK T_MINUS12_LK T_MINUS13_LK T_MINUS14_LK T_MINUS15_LK T_MINUS16_LK T_MINUS17_LK T_MINUS18_LK T_MINUS19_LK T_MINUS20_LK T_MINUS21_LK T_MINUS22_LK T_MINUS23_LK T_MINUS24_LK T_MINUS25_LK T_MINUS26_LK T_MINUS27_LK T_MINUS28_LK T_MINUS29_LK T_MINUS30_LK T_MINUS31_LK T_MINUS32_LK T_MINUS33_LK T_MINUS34_LK MANUF_REG DEV_REG GPI_REG Register Name Top Block Lock Register (Block 49) Top Block[-01] Lock Register (Block 48) Top Block[-02] Lock Register (Block 47) Top Block[-03] Lock Register (Block 46) Top Block[-04] Lock Register (Block 45) Top Block[-05] Lock Register (Block 44) Top Block[-06] Lock Register (Block 43) Top Block[-07] Lock Register (Block 42) Top Block[-08] Lock Register (Block 41) Top Block[-09] Lock Register (Block 40) Top Block[-10] Lock Register (Block 39) Top Block[-11] Lock Register (Block 38) Top Block[-12] Lock Register (Block 37) Top Block[-13] Lock Register (Block 36) Top Block[-14] Lock Register (Block 35) Top Block[-15] Lock Register (Block 34) Top Block[-16] Lock Register (Block 33) Top Block[-17] Lock Register (Block 32) Top Block[-18] Lock Register (Block 31) Top Block[-19] Lock Register (Block 30) Top Block[-20] Lock Register (Block 29) Top Block[-21] Lock Register (Block 28) Top Block[-22] Lock Register (Block 27) Top Block[-23] Lock Register (Block 26) Top Block[-24] Lock Register (Block 25) Top Block[-25] Lock Register (Block 24) Top Block[-26] Lock Register (Block 23) Top Block[-27] Lock Register (Block 22) Top Block[-28] Lock Register (Block 21) Top Block[-29] Lock Register (Block 20) Top Block[-30] Lock Register (Block 19) Top Block[-31] Lock Register (Block 18) Top Block[-32] Lock Register (Block 17) Top Block[-33] Lock Register (Block 16) Top Block[-34] Lock Register (Block 15 to 0) Manufacturer Code Register Device Code Register General Purpose Input Register Memory Address FFBFC002h FFBFA002h FFBF8002h FFBF0002h FFBE0002h FFBD0002h FFBC0002h FFBB0002h FFBA0002h FFB90002h FFB80002h FFB70002h FFB60002h FFB50002h FFB40002h FFB30002h FFB20002h FFB10002h FFB00002h FFAF0002h FFAE0002h FFAD0002h FFAC0002h FFAB0002h FFAA0002h FFA90002h FFA80002h FFA70002h FFA60002h FFA50002h FFA40002h FFA30002h FFA20002h FFA10002h FFA00002h FFBC0000h FFBC0001h FFBC0100h Default Value 01h 01h 01h 01h 01h 01h 01h 01h 01h 01h 01h 01h 01h 01h 01h 01h 01h 01h 01h 01h 01h 01h 01h 01h 01h 01h 01h 01h 01h 01h 01h 01h 01h 01h 01h 20h 30h N/A Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R
Note: 1. This map is referred to the boot memory (ID0-ID3 floating or driven Low, VIL, and A21,A23-A25 set to `1').
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Table 15. Lock Register Bit Definitions(1)
Bit 7-3 `1' 2 Read-Lock `0' Bit Name Value Reserved Bus Read operations in this Block always return 00h. Bus read operations in this Block return the Memory Array contents. (Default value). Changes to the Read-Lock bit and the Write-Lock bit cannot be performed. Once a `1' is written to the Lock-Down bit it cannot be cleared to `0'; the bit is always reset to `0' following a Reset (using RP or INIT) or after power-up. Read-Lock and Write-Lock can be changed by writing new values to them. (Default value). Program and Block Erase operations in this Block will set an error in the Status Register. The memory contents will not be changed. (Default value). Program and Block Erase operations in this Block are executed and will modify the Block contents. Function
`1' 1 Lock-Down `0' `1' 0 Write-Lock `0'
Note: 1. Applies to Top Block Lock Register (T_BLOCK_LK) and Top Block [-1] Lock Register (T_MINUS01_LK) to Top Block [-34] Lock Register (T_MINUS34_LK).
Table 16. General Purpose Input Register Definition (1)
Bit 7-5 `1' 4 GPI4 `0' `1' 3 GPI3 `0' `1' 2 GPI2 `0' `1' 1 GPI1 `0' `1' 0 GPI0 `0' Input Pin GPI0 is at VIL Input Pin GPI1 is at VIL Input Pin GPI0 is at VIH Input Pin GPI2 is at VIL Input Pin GPI1 is at VIH Input Pin GPI3 is at VIL Input Pin GPI2 is at VIH Input Pin GPI4 is at VIL Input Pin GPI3 is at VIH Bit Name Value Reserved Input Pin GPI4 is at VIH Function
Note: 1. Applies to the General Purpose Input Register (GPI_REG).
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Lock Registers The Lock Registers control the protection status of the Blocks. Each Block has its own Lock Register. Blocks 0 to 15 have the same Lock Register. Three bits within each Lock Register control the protection of each block, the Write Lock Bit, the Read Lock Bit and the Lock Down Bit. The Lock Registers can be read and written, though care should be taken when writing as, once the Lock Down Bit is set, `1', further modifications to the Lock Register cannot be made until cleared, to `0', by a reset or power-up. See Table 15 for details on the bit definitions of the Lock Registers. Write Lock. The Write Lock Bit determines whether the contents of the Block can be modified (using the Program or Block Erase Command). When the Write Lock Bit is set, `1', the block is write protected; any operations that attempt to change the data in the block will fail and the Status Register will report the error. When the Write Lock Bit is reset, `0', the block is not write protected through the Lock Register and may be modified unless write protected through some other means. When V PP is less than VPPLK all blocks are protected and cannot be modified, regardless of the state of the Write Lock Bit. If Top Block Lock, TBL, is Low, V IL, then the Top Block (Block 49) is write protected and cannot be modified. Similarly, if Write Protect, WP, is Low, VIL, then the Blocks 0 to 48 are write protected and cannot be modified. After power-up or reset the Write Lock Bit is always set to `1' (write protected). Read Lock. The Read Lock bit determines whether the contents of the Block can be read (from Read mode). When the Read Lock Bit is set, `1', the block is read protected; any operation that attempts to read the contents of the block will read 00h instead. When the Read Lock Bit is reset, `0', read operations in the Block return the data programmed into the block as expected. After power-up or reset the Read Lock Bit is always reset to `0' (not read protected). Lock Down. The Lock Down Bit provides a mechanism for protecting software data from simple hacking and malicious attack. When the Lock Down Bit is set, `1', further modification to the Write Lock, Read Lock and Lock Down Bits cannot be performed. A reset or power-up is required before changes to these bits can be made. When the Lock Down Bit is reset, `0', the Write Lock, Read Lock and Lock Down Bits can be changed. General Purpose Input Register The General Purpose Input Register holds the state of the General Purpose Input pins, GPI0GPI4. When this register is read, the state of these pins is returned. This register is read-only and writing to it has no effect. The signals on the General Purpose Input pins should remain constant throughout the whole Bus Read cycle in order to guarantee that the correct data is read.
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Table 17. LPC Interface AC Measurement Conditions
Parameter VCC Supply Voltage Load Capacitance (CL) Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages Value 3.0 to 3.6 10 1.4 0.2 VCC and 0.6 VCC 0.4 VCC Unit V pF ns V V
Figure 6. LPC Interface AC Testing Input Output Waveforms
0.6 VCC 0.4 VCC 0.2 VCC Input and Output AC Testing Waveform
IO < ILO
IO > ILO
IO < ILO
Output AC Tri-state Testing Waveform
AI03404
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Table 18. A/A Mux Interface AC Measurement Conditions
Parameter VCC Supply Voltage Load Capacitance (CL) Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages Value 3.0 to 3.6 30 10 0 to 3 1.5 Unit V pF ns V V
Figure 7. A/A Mux Interface AC Testing Input Output Waveform
3V 1.5V 0V
AI01417
Table 19. Impedance (TA = 25 C, f = 1 MHz)
Symbol CIN(1) CCLK(1) LPIN(2) Parameter Input Capacitance Clock Capacitance Recommended Pin Inductance Test Condition VIN = 0V VIN = 0V 3 Min Max 13 12 20 Unit pF pF nH
Note: 1. Sampled only, not 100% tested. 2. See PCI Specification.
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Table 20. DC Characteristics (TA = 0 to 70C or -20 to 85C; VCC = 3.0 to 3.6V)
Symbol VIH Parameter Input High Voltage Interface LPC A/A Mux LPC Input Low Voltage INIT Input High Voltage INIT Input Low Voltage Input Leakage Current IC, IDx Input Leakage Current IC, IDx Input Pull Low Resistor LPC VOH Output High Voltage A/A Mux LPC VOL ILO VPP1 VPPH VPPLK(1) VLKO(1) ICC1 Output Low Voltage A/A Mux Output Leakage Current VPP Voltage VPP Voltage (Fast Program/Fast Erase) VPP Lockout Voltage VCC Lockout Voltage Supply Current (Standby) LPC LFRAME = 0.9 VCC, VPP = VCC All other inputs 0.9 VCC to 0.1 VCC VCC = 3.6V, f(CLK) = 33MHz LFRAME = 0.1 VCC, VPP = VCC All other inputs 0.9 VCC to 0.1 VCC VCC = 3.6V, f(CLK) = 33MHz VCC = VCC max, VPP = VCC f(CLK) = 33MHz IOUT = 0mA G = VIH, f = 6MHz Program/Erase Controller Active VPP > VCC VPP = VCC VPP = 12V 5% IOL = 1.8mA 0V VOUT VCC 3 11.4 1.5 1.8 2.3 100 0.45 10 3.6 12.6 V IOH = -100A IOL = 1.5mA VCC - 0.4 0.1 VCC V V IOH = -500A A/A Mux LPC LPC 0V VIN VCC IC, ID0, ID1, ID2, ID3 = VCC 20 0.9 VCC Test Condition Min 0.5 VCC 0.7 VCC -0.5 -0.5 1.35 -0.5 Max VCC + 0.5 VCC + 0.3 0.3 VCC 0.8 VCC + 0.5 0.2 VCC 10 200 100 Unit V V V V V V
VIL VIH(INIT) VIL(INIT) ILI(2) ILI2 RIL
A A
k V
A
V V V V
A
ICC2
Supply Current (Standby) Supply Current (Any internal operation active) Supply Current (Read) Supply Current (Program/Erase) VPP Supply Current (Read/Standby) VPP Supply Current (Program/Erase active)
LPC
10
mA
ICC3 ICC4 ICC5(1) IPP
LPC A/A Mux A/A Mux
60 20 20 400 5 15
mA mA mA
A A
mA
IPP1(1)
Note: 1. Sampled only, not 100% tested. 2. Input leakage currents include High-Z output leakage for all bi-directional buffers with tri-state outputs.
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M50LPW116
Table 21. LPC Interface Clock Characteristics (TA = 0 to 70C or -20 to 85C; VCC = 3.0 to 3.6V)
Symbol tCYC tHIGH tLOW Parameter CLK Cycle Time(1) CLK High Time CLK Low Time CLK Slew Rate peak to peak Max 4 V/ns Test Condition Min Min Min Min Value 30 11 11 1 Unit ns ns ns V/ns
Note: 1. Devices on the PCI Bus must work with any clock frequency between DC and 33MHz. Below 16MHz devices may be guaranteed by design rather than tested. Refer to PCI Specification.
Figure 8. LPC Interface Clock Waveform
tCYC tHIGH 0.6 VCC 0.5 VCC 0.4 VCC 0.3 VCC 0.2 VCC
AI03403
tLOW
0.4 VCC, p-to-p (minimum)
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M50LPW116
Table 22. LPC Interface AC Signal Timing Characteristics (TA = 0 to 70C or -20 to 85C; V CC = 3.0 to 3.6V)
Symbol PCI Symbol tval ton toff tsu th Parameter Test Condition Min CLK to Data Out Max CLK to Active (Float to Active Delay) CLK to Inactive (Active to Float Delay) Input Set-up Time(2) Input Hold Time(2) Min Max Min Min 11 2 28 7 0 ns ns ns ns ns Value 2 Unit ns
tCHQV tCHQX(1) tCHQZ tAVCH tDVCH tCHAX tCHDX
Note: 1. The timing measurements for Active/Float transitions are defined when the current through the pin equals the leakage current specification. 2. Applies to all inputs except CLK.
Figure 9. LPC Interface AC Signal Timing Waveforms
CLK tCHQV tCHQZ tCHQX LAD0-LAD3 VALID OUTPUT DATA FLOAT OUTPUT DATA tCHDX VALID VALID INPUT DATA
AI04431
tDVCH
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M50LPW116
Table 23. Reset AC Characteristics (TA = 0 to 70C or -20 to 85C; VCC = 3.0 to 3.6V)
Symbol tPLPH tPLRH Parameter RP or INIT Reset Pulse Width Program/Erase Inactive RP or INIT Low to Reset Program/Erase Active RP or INIT Slew Rate(1) tPHFL tPHWL tPHGL RP or INIT High to LFRAME Low RP High to Write Enable or Output Enable Low Rising edge only LPC Interface only A/A Mux Interface only Max Min Min Min 30 50 30 50 Test Condition Min Max Value 100 100 Unit ns ns s mV/ns s s
Note: 1. See Chapter 4 of the PCI Specification.
Figure 10. Reset AC Waveforms
RP, INIT tPLPH W, G, LFRAME tPHWL, tPHGL, tPHFL
tPLRH
RB
AI04432
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M50LPW116
Table 24. A/A Mux Interface Read AC Characteristics (TA = 0 to 70C or -20 to 85C; VCC = 3.0 to 3.6V)
Symbol tAVAV tAVCL tCLAX tAVCH tCHAX tCHQV(1) tGLQV(1) tPHAV tGLQX tGHQZ tGHQX Parameter Read Cycle Time Row Address Valid to RC Low RC Low to Row Address Transition Column Address Valid to RC high RC High to Column Address Transition RC High to Output Valid Output Enable Low to Output Valid RP High to Row Address Valid Output Enable Low to Output Transition Output Enable High to Output Hi-Z Output Hold from Output Enable High Test Condition Min Min Min Min Min Max Max Min Min Max Min Value 250 50 50 50 50 150 50 1 0 50 0 Unit ns ns ns ns ns ns ns s ns ns ns
Note: 1. G may be delayed up to tCHQV - t GLQV after the rising edge of RC without impact on t CHQV.
Figure 11. A/A Mux Interface Read AC Waveforms
tAVAV A0-A10 tAVCL tCLAX RC tCHQV G tGLQV tGLQX DQ0-DQ7 tGHQZ tGHQX VALID ROW ADDR VALID COLUMN ADDR VALID tAVCH tCHAX NEXT ADDR VALID
W tPHAV RP
AI03406
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M50LPW116
Table 25. A/A Mux Interface Write AC Characteristics (TA = 0 to 70C or -20 to 85C; VCC = 3.0 to 3.6V)
Symbol tWLWH tDVWH tWHDX tAVCL tCLAX tAVCH tCHAX tWHWL tCHWH tVPHWH(1) tWHGL tWHRL tQVVPL(1,2) Parameter Write Enable Low to Write Enable High Data Valid to Write Enable High Write Enable High to Data Transition Row Address Valid to RC Low RC Low to Row Address Transition Column Address Valid to RC High RC High to Column Address Transition Write Enable High to Write Enable Low RC High to Write Enable High VPP High to Write Enable High Write Enable High to Output Enable Low Write Enable High to RB Low Output Valid, RB High to VPP Low Test Condition Min Min Min Min Min Min Min Min Min Min Min Min Min Value 100 50 5 50 50 50 50 100 50 100 30 0 0 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
Note: 1. Sampled only, not 100% tested. 2. Applicable if VPP is seen as a logic input (V PP < 3.6V).
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M50LPW116
Figure 12. A/A Mux Interface Write AC Waveforms
Write erase or program setup A0-A10 R1 C1 tCLAX tAVCL RC tWHWL tWLWH W tVPHWH G tWHRL RB tQVVPL VPP tDVWH DQ0-DQ7 DIN1 DIN2 tWHDX VALID SRD
AI04194
Write erase confirm or valid address and data R2 tAVCH tCHAX C2
Automated erase or program delay
Read Status Register Data
Ready to write another command
tCHWH
tWHGL
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M50LPW116
Figure 13. Program Flowchart and Pseudo Code
Start
Write 40h or 10h
Write Address & Data
Program command: - write 40h or 10h - write Address & Data (memory enters read status state after the Program command)
NO Read Status Register Suspend NO YES Suspend Loop
do: -read Status Register if Program/Erase Suspend command given execute suspend program loop
b7 = 1 YES b3 = 0 YES b4 = 0 YES LPC Interface Only b1 = 0 YES End
while b7 = 1 NO
VPP Invalid Error (1, 2)
If b3 = 1, VPP invalid error: - error handler
NO
Program Error (1, 2)
If b4 = 1, Program error: - error handler
NO
Program to Protected Block Error (1, 2)
If b1 = 1, Program to protected block error: - error handler
AI04433
Note: 1. A Status check of b1 (Protected Block), b3 (V PP invalid) and b4 (Program Error) can be made after each Program operation by following the correct command sequence. 2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.
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M50LPW116
Figure 14. Quadruple Byte Program Flowchart and Pseudo Code (A/A Mux Interface Only)
Start
Write 30h
Write Address 1 & Data 1 (3)
Write Address 2 & Data 2 (3)
Quadruple Byte Program command: - write 30h - write Address 1 & Data 1 (3) - write Address 2 & Data 2 (3) - write Address 3 & Data 3 (3) - write Address 4 & Data 4 (3) (memory enters read status state after the Quadruple Byte Program command)
Write Address 3 & Data 3 (3)
Write Address 4 & Data 4 (3) do: - read Status Register if Program/Erase Suspend command given execute suspend program loop YES Suspend Loop while b7 = 1 NO
NO Read Status Register Suspend NO
b7 = 1 YES b3 = 0 YES b4 = 0 YES End
VPP Invalid Error (1, 2)
If b3 = 1, VPP invalid error: - error handler
NO
Program Error (1, 2)
If b4 = 1, Program error: - error handler
AI03982
Note: 1. A Status check of b3 (VPP invalid) and b4 (Program Error) can be made after each Program operation by following the correct command sequence. 2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations. 3. Address 1, Address 2, Address 3 and Address 4 must be consecutive addresses differing only for address bits A0 and A1.
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M50LPW116
Figure 15. Program Suspend and Resume Flowchart and Pseudo Code
Start
Write B0h
Write 70h
Program/Erase Suspend command: - write B0h - write 70h do: - read Status Register
Read Status Register
b7 = 1 YES b2 = 1 YES Write a read Command
NO
while b7 = 1
NO
Program Complete
If b2 = 0 Program completed
Read data from another address
Write D0h
Write FFh
Program Continues
Read Data
Program/Erase Resume command: - write D0h to resume the program - if the Program operation completed then this is not necessary. The device returns to Read as normal (as if the Program/Erase suspend was not issued).
AI03408
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M50LPW116
Figure 16. Chip Erase Flowchart and Pseudo Code (A/A Mux Interface Only)
Start
Write 80h
Chip Erase command: - write 80h - write 10h (memory enters read Status Register after the Chip Erase command)
Write 10h do: - read Status Register
Read Status Register
b7 = 1
NO
YES b3 = 0 YES b4, b5 = 0 YES b5 = 0 YES End NO Erase Error (1) NO Command Sequence Error (1) NO VPP Invalid Error (1)
while b7 = 1
If b3 = 1, VPP invalid error: - error handler
If b4, b5 = 1, Command sequence error: - error handler
If b5 = 1, Erase error: - error handler
AI04195
Note: 1. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.
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M50LPW116
Figure 17. Block Erase Flowchart and Pseudo Code
Start
Write 20h
Write Block Address & D0h
Block Erase command: - write 20h - write Block Address & D0h (memory enters read Status Register after the Block Erase command)
Read Status Register
NO Suspend
do: - read Status Register - if Program/Erase Suspend command given execute suspend erase loop YES
b7 = 1
NO
Suspend Loop while b7 = 1
YES b3 = 0 YES b4, b5 = 0 YES b5 = 0 YES LPC Interface Only b1 = 0 YES End NO Erase to Protected Block Error (1) NO Erase Error (1) NO Command Sequence Error (1) NO VPP Invalid Error (1)
If b3 = 1, VPP invalid error: - error handler
If b4, b5 = 1, Command sequence error: - error handler
If b5 = 1, Erase error: - error handler
If b1 = 1, Erase to protected block error: - error handler
AI04434
Note: 1. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.
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M50LPW116
Figure 18. Erase Suspend & Resume Flowchart and Pseudo Code
Start
Write B0h
Write 70h
Program/Erase Suspend command: - write B0h - write 70h do: - read Status Register
Read Status Register
b7 = 1 YES b6 = 1 YES
NO
while b7 = 1
NO
Erase Complete
If b6 = 0, Erase completed
Read data from another block or Program
Write D0h
Write FFh
Erase Continues
Read Data
Program/Erase Resume command: - write D0h to resume erase - if the Erase operation completed then this is not necessary. The device returns to Read as normal (as if the Program/Erase suspend was not issued).
AI03410
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M50LPW116
Table 26. Ordering Information Scheme
Example: Device Type M50 Architecture LP = Low Pin Count Interface Operating Voltage W = 3.0 to 3.6V Device Function 116 = 16 Mbit (2Mb x8), Boot Block Package N = TSOP40: 10 x 20 mm Temperature Range 1 = 0 to 70 C 5 = -20 to 85C Option T = Tape & Reel Packing
M50LPW116
N
1
T
For a list of available options or for further information on any aspect of this device, please contact the ST Sales Office nearest to you.
Table 27. Revision History
Date September 2001 12-Dec-2001 16-Jan-2002 01-Mar-2002 30-Jul-2002 22-Nov-2002 13-Feb-2003 Version -01 -02 -03 -04 -05 5.1 5.2 First Issue Extensions to the descriptions on Quadruple Byte Programming Device code announced: 30h RFU pins must be left disconnected Quadruple Byte Mode, in LPC mode, removed Revision numbering modified: a minor revision will be indicated by incrementing the digit after the dot, and a major revision, by incrementing the digit before the dot (revision version 05 equals 5.0). Document promoted to Product Preview. Datasheet promoted from Product Preview to Preliminary Data status. Revision Details
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M50LPW116
TSOP40 - 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Outline
A2
1 N
e E B
N/2
D1 D
A CP
DIE
C
TSOP-a
A1
L
Note: Drawing is not to scale.
TSOP40 - 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Mechanical Data
millimeters Symbol Typ A A1 A2 B C D D1 E e L N CP 0.500 0.050 0.950 0.170 0.100 19.800 18.300 9.900 - 0.500 0 40 0.100 Min Max 1.200 0.150 1.050 0.270 0.210 20.200 18.500 10.100 - 0.700 5 0.0197 0.0020 0.0374 0.0067 0.0039 0.7795 0.7205 0.3898 - 0.0197 0 40 0.0039 Typ Min Max 0.0472 0.0059 0.0413 0.0106 0.0083 0.7953 0.7283 0.3976 - 0.0276 5 inches
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M50LPW116
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics All other names are the property of their respective owners (c) 2003 STMicroelectronics - All Rights Reserved STMicroelectronics group of companies Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. www.st.com
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